1. Field of the Invention
The present invention relates to high-frequency devices including high-frequency switching circuits and being applicable to, for example, cellular phones.
2. Description of the Related Art
For example, cellular phones have communicated with each other using high-frequency signals having frequencies in the range of 800 MHz to 2.3 GHz. In such relatively high frequencies, compound semiconductors such as GaAs, which has high electron mobility, in place of known Group IV semiconductors, such as a Si semiconductor, have often been used for power amplifiers (PAs) for amplifying transmission powers, low-noise amplifiers (LNA) for amplifying received signals, and switching circuits for switching signals, in view of high-frequency characteristics.
Devices including high-frequency integrated circuits containing the compound semiconductors such as GaAs have satisfactory high-frequency characteristics when the devices are driven at low voltages. However, as trends toward lower voltage and higher performance grow, there have been further stringent demands for the improvement of frequency characteristics, in particular, a reduction in distortion of switching circuits that correspond to third-generation (3G) cellular phones and that enable simultaneous transmission and reception.
For example, as switching circuits for switching antennae in cellular phones, from the above-described reasons, switch monolithic microwave integrated circuits (switch MMICs) including field-effect transistors (FETs) each containing a GaAs compound semiconductor have often been used. Such antenna-switching circuits are required to meet stringent requirements: low loss, low distortion, and the like at a low operating voltage, e.g., at an operating voltage of 2.6 V.
Various switch ICs have been proposed (for example, see Uda. A Very High Isolation GaAs SPDT Switch IC Seald in an Ultra-compact Plastic Package. IEEE GaAs IC Symposium 1995, pp. 132-135H).
FIG. 12 is a circuit diagram showing the most basic switching circuit including junction gate field-effect transistors (J-FETs) each containing, for example, a GaAs compound semiconductor. In this case, a first FET1 and a second FET2 are disposed on a common GaAs substrate, the first FET1 and the second FET2 each being a J-FET. The source of the first FET1 is connected to the drain of the second FET2. One end of the current channel of the first FET1 is connected to a first input/output terminal I/O1 with a capacitor C1, the other end is connected to a second input/output terminal I/O2 via a capacitor C2. One end of the current channel of the second FET2 is connected to a ground terminal GND via a capacitor C3. Thereby, the circuit is DC-decoupled from the exterior.
The gate of the first FET1 is connected to a control signal input terminal CTL1 via a resistor R1. The gate of the second FET2 is connected to a control signal input terminal CTL2 via a resistor R2. The midpoint of the current channel between the source of the first FET1 and the drain of the second FET2 is connected to a DC bias terminal via a resistor R3.
In this switching circuit 11, for example, a logic circuit applies a bias voltage of 2 V to the switching circuit via the resistor R3. For example, when a high voltage, e.g., 3 V, is applied to the terminal CTL1, the gate bias (with respect to the drain and source) of the first FET1 is 1 V. As a result, the FET1 is ON. On the other hand, for example, when a low voltage, e.g., 0 V, is applied to the terminal CTL2, the gate bias (with respect to the drain and source) of the second FET2 is −2 V. As a result, the FET2 is OFF. Therefore, the channel between the terminals I/O1 and I/O2 is ON, that is, the switching circuit is ON.
In contrast, for example, when a low voltage, e.g., 0 V, is applied to the terminal CTL1, the gate bias (with respect to the drain and source) of the first FET1 is −2 V. As a result, the FET1 is OFF. On the other hand, for example, when a high voltage, e.g., 3 V, is applied to the terminal CTL2, the gate bias (with respect to the drain and source) of the second FET2 is 1 V. As a result, the FET2 is ON. Therefore, the channel between the terminals I/O1 and I/O2 is OPEN. That is, the signal channel is high-frequency-short-circuited, thus ensuring further isolation.
FIG. 13 is a schematic cross-sectional view of a mounted high-frequency device including a known switch MMIC having the above-described switching circuit.
In this case, a switch MMIC 102 is mounted on a conductive die pad 101. Electrodes of the MMIC 102 are connected to first and second high-frequency input/output terminals I/O1 and I/O2, at which a high frequency is inputted or outputted, with lead wires 104 or the like. The switch MMIC 102, the conductive die pad 101, and the first and second high-frequency input/output terminals I/O1 and I/O2 are covered with a resin mold 105 to form a packaged integrated circuit (IC). The packaged IC is disposed on a circuit board 100. The conductive die pad 101 and the first and second high-frequency input/output terminals I/O1 and I/O2 are electrically connected to the circuit board 100.
The die pad 101 is formed of a conductive metal layer and is grounded.
FIG. 14 is a schematic fragmentary cross-sectional view of a junction gate field-effect transistor (J-FET) containing, for example, GaAs. In this case, a lightly doped semiconductor layer constituting a channel-forming region 107 is disposed on a GaAs substrate 106 composed of bulk GaAs and is disposed between, for example, two heavily doped N regions, i.e., a source region 108S and a drain region 108D. A drain electrode D, a source electrode S, and a gate electrode G are in ohmic contact with the drain region, the source region, and the gate region, respectively.
The presence of the semiinsulating GaAs substrate 106 disposed directly below the channel-forming region 107, i.e., remote from a gate region 109, minimizes leakage of a signal.